Programmable logic devices (“PLDs”) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (“FPGA”), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAMs”), multipliers, digital signal processing blocks (“DSPs”), processors, clock managers, delay lock loops (“DLLs”), and so forth. Notably, as used herein, “include” and “including” mean including without limitation.
One such FPGA is the Xilinx Virtex® FPGA available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124. Another type of PLD is the Complex Programmable Logic Device (“CPLD”). A CPLD includes two or more “function blocks” connected together and to input/output (“I/O”) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (“PLAs”) and Programmable Array Logic (“PAL”) devices. Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, for example, using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable.
For purposes of clarity, FPGAs are described below though other types of PLDs may be used. FPGAs may include one or more embedded microprocessors. For example, a microprocessor may be located in an area reserved for it, generally referred to as a “processor block.”
Recently, FPGAs have been used for digital video processing. In order to more conveniently send video over limited bandwidth networks, video compression is used. There are many known types of video compression, including that associated with Motion Pictures Expert Group (“MPEG”), among others. For purposes of clarity by way of example and not limitation, MPEG compression and decompression is described below, although other types of compression may be used.
Generally, a video sequence includes a number of pictures or frames. Frames in a sequence may be substantially similar, and thus contain a significant amount of redundant information. In video compression, this redundant information may effectively be removed by using a reference frame and a number of residual frames. As residual frames are indexed to a reference frame, they may contain less information than the reference frame. Accordingly, they may be encoded at a lower bit rate with the same quality as the original frames from which they were obtained.
In MPEG, frames are processed in groups of pictures (“GOPs”). A reference frame, which is an intracoded frame (“I-frame” or “I-picture”) is combined with predicted frames (“P-frames or P-pictures”). One or more P-frames may be predicted from a preceding I-frame or P-frame. Furthermore, frames may be predicted from future frames. Such predicted frames from future frames may be predicted from two directions, such as for example from an I-frame and a P-frame that respectively immediately precede and follow the bidirectionally predicted frame. Conventionally, bidirectionally predicted frames are called “B-frames” or “B-pictures.”
Frames may be partitioned into blocks, each of which is an array of pixels. These blocks may be grouped together in what is sometimes referred to as a “macroblock.” Groups of macroblocks, where each group is associated with a frame, are known as “slices.” Each block is predicted from a block of equal size in a reference frame. Blocks are not transformed apart from the original frame other than being shifted to a position of a predicted block.
For intra-frame blocks (“intra blocks”), conventional AC-DC prediction has been used, such as specified by MPEG. In MPEG, a block is a matrix of 8-by-8 pixels, which may be a either adjacent luminance or chrominance samples, or corresponding DCT coefficients as is known. A block may be coded to represent an image sample, namely an intra block, or may be coded to represent a prediction-error, namely an inter block or non-intra block. Examples of inter blocks include blocks coded for motion compensation or motion estimation. For example, to lower energy residue of a frame, such as an I-frame, P-frame, or B-frame, AC-DC prediction may be used to predict either a first column or a first row of an intra block. Thus, correlation in a frequency domain may be exploited to predict either a first column or a first row of an intra block by using one or more neighboring intra blocks of the same slice. Other details regarding MPEG video encoding and decoding are not described, as they are well known.
MPEG-4 is for low bandwidth applications, such as for approximately 64 kilobits per second for example. Applications generally associated with MPEG-4 include video associated with portable wireless devices. These devices tend to have significant power consumption limitations and space limitations. Furthermore, portable wireless devices may have significant limitations on computing capability, and may be significantly constrained with respect to real-time handling of video decoding at a system clock rate. Examples of MPEG-4 decoders include the Mobile Multimedia Systems (“MoMuSys”) reference decoder published by the International Organization for Standardization (“ISO”). The MoMuSys reference decoder is capable of handling any MPEG-4 Natural Video stream, including multiple video streams. A Simple Profile, as well as an Advanced Simple Profile, is a subset of MPEG-4 Natural Video. Moreover, others have suggested implementing MPEG-4 encoders in programmable logic of FPGAS, such as an MPEG-4 Simple Profile encoder available from Barco-Silex of Belgium (www.barcodesignservices.com).
Accordingly, it would be desirable and useful to provide a less complex form of AC-DC prediction for low bandwidth video. Furthermore, it would be desirable and useful to provide a form of AC-DC prediction that would be reasonable for implementation in an FPGA or other integrated circuit.